Like area and power, latency is an important design parameter, accurately measuring real time latency is critical to low latency applications. However, conventional techniques to measure latency have disadvantages. According to one conventional technique, a difference between read and write pointers is averaged. While it is assumed that latency through the data path is fixed, and only variable is for first-in, first-out (FIFO) blocks and Gearbox FIFO blocks, this technique calculates the latency through FIFOs as an average of difference between read and write pointers over a period of time. This average latency is added with the fixed latency of the path. However, such latency measurements are not accurate, as there are many unknown latency components in a data path other than FIFOs.
According to another technique which is based upon a fixed marker latency measurement, a fixed latency marker is sent to a transmit (TX) data path. A counter is incremented until the data is received back at the receiver. However, according to this technique, the latency is accurate only up to a number of cycles. This technique is also complicated by data recovery problems in clock and data recovery (CDR). Further, differences in data alignment in the receiver versus the transmitter complicate the recognition of the latency marker and calculation of latency. Finally, different phases of the transmitter and receiver clocks can also reduce the accuracy of the latency measurement.
Accordingly, methods and circuits that more accurately measure latency in an integrated circuit are beneficial.